An integrated circuit may contain an npn bipolar junction transistor (BJT) and an n-channel metal oxide semiconductor (NMOS) transistor, for example to provide analog functions and logic functions, respectively. Source and drain regions of the NMOS transistor and the emitter region of the npn BJT may be formed concurrently to reduce fabrication costs. Process steps for forming the source and drain regions and the emitter region may include ion implanting arsenic at a dose above 6×1013 atoms/cm2, for example to attain a desired resistance in the NMOS transistor. The ion implanted arsenic may form end-of-range defects, sometimes referred to as dislocation loops, at a density higher than 1×107 defects/cm2, in the emitter region. The end-of-range defects may adversely affect performance of the npn BJT, for example by reducing current gain, also referred to as hfe. Subsequent thermal anneals may not be sufficient to reduce the end-of-range defects to a desired level, because attaining desired levels of performance and yield in instances of the NMOS transistor may be achieved by limiting the total thermal profile of the integrated circuit after the arsenic ion implant step. Other devices in an integrated circuit which receives an ion implant at a dose which produces more than 1×107 end-of-range defects/cm2, for example to provide electrically active dopants or to amorphize the substrate of the integrated circuit, may experience degradation of performance parameters due to the end-of-range defects.